Scale conversion apparatus

ABSTRACT

A linear scale converter for converting an input train of electrical pulses each of which represents a required elemental movement (e.g., of a machine tool) of fixed length expressed in a particular scale, such as the Imperial scale, to an output train of pulses each of which represents such movement but expressed in another scale, such as the Metric scale, where the output/input scale ratio is D/N, includes apparatus for defining each input group of N pulses and adding algebraically to it (D-N) pulses at locations spaced approximately evenly over the group, thereby providing an output group of D pulses.

[ 51 Mar. 7, 1972 SCALE CONVERSION APPARATUS inventors: AlexanderTurnbull Shepherd, Craigleith Crescent; Laurence Philip Smith, Penicuik;Lockhart Taylor, Hailes Gardens, all of Scotland Assignee: Ferranti,Limited, Hollinwood, Lancashire, England Filed: Sept. 16, 1969 Appl.No.: 858,274

Foreign Application Priority Data [56] References Cited UNITED STATESPATENTS 2,566,085 8/1951 Green ..235/l56 3,404,343 10/ 1968 Strand..235/92 PL 3,209,130 9/1965 Schmidt.. ..235/92 PL 3,549,870 12/1970 Lay..235/92 PL Primary Examiner-Maynard R. Wilbur Assistant Examiner-JosephM. Thesz, Jr. Attorney-Cameron, Kerkam & Sutton [5 7] ABSTRACT A linearscale converter for converting an input train of elec- Sept. 19, 1968Great Britain ..44,476/68 "ical Pluses each which rePramts a requiredelement movement (e.g., of a machine tool) of fixed length expressed ina particular scale, such as the Imperial scale, to an output U.S.Cl...235/92 PL, 328/44, 235/92 R, train of pulses each of which representssuch movement but 235/92 235/92 PE expressed in another scale, such asthe Metric scale, where the Int. Cl ..G06m 3/14, H03k 21/36 output/inputScale ratio is I includes apparatus for defim Field of S arch 235/92, 2/4 34 ing each input group of N pulses and adding algebraically to it(D-N) pulses at locations spaced approximately evenly over the group,thereby providing an output group of D pulses.

5 Claims, 18 Drawing Figures ADD Q SUB iii i II 12 v COUNTER r COUNTERHill 24 I3 DET ECTO R 14 I5 7 v I 6 23 22 PULSE A G E N ER ATOR PatentedMarch 7, 1972 V 8 Sheets-Sheet 1 (COUNTER II H DETECTOR A ADD SUB 5 I2I] f COUNTER PULSE GENERATOR Patented March 7, 1972 3,648,030

8 Sheets-Sheet 2 Patented March 7, 1972 8 Sheets-Sheet 4 Inventor A Homey Patented March 7, 1972 3,648,030

8 Sheets-Sheet 5 P30 P3 P32 P33 @0132) W U TL I ((15) E I (c) (wa i I 05l STAGE (a) (R03) W (e) (FROM l6) (P) (FROM 96) P32 (9) (FROM I7) fiPsz' Inventor (h) (23) WW P30 P31 P32 P32' P33 By A Home y 8Sheets-Sheet 6 In oenlor A Home y Patented March 7, 1972 Patented March7, 1912 3,648,030

8 Sheets-Sheet a lnvenlor .4 Horny SCALE CONVERSION APPARATUS Thisinvention relates to scale conversion apparatus for converting an inputseries sequence of electrical pulses of either sign significance,representing equal incremental quantities expressed in a particularmeasurement scale, to an output series sequence of pulses expressed inanother scale.

The invention has especial application where the scales are the imperialand metric linear scales. The invention will accordingly be described inthat connection; it should however be understood that the invention isnot confined to that particular use but is applicable where the quantityconcerned is other than a linear measurement and where the scalescompared are other than the imperial and the metric.

An object of the invention is-to provide scale conversion apparatus forthe purpose stated.

In accordance with the present invention, scale conversion apparatus forthe purpose stated where the output/input scale ratio 'is D/N includesconversion means for effectively adding algebraically to each group ofinput pulses totaling N algebraically (D-N) single pulses of sensedependence on the sign of (D-N) at locations spaced from one anotherwithin the group and'from the nearest corresponding single pulses of theimmediately adjacent group(s) at intervals of approximately N/(D-N)pulses of the input sequence, the sign of (D-N) being here ignored,thereby deriving as said output sequence and output group totaling Dpulses algebraically for each of said input groups. When reference ismade to (D-N), it should be apparent that the expression means D minus Nand not D to N or D through N.

The expression effectively" adding algebraically should be understood toinclude not only the case where (D-N) is negative and the said singlepulses are inserted negatively in the input group but also the casewhere (D-N) is negative and no pulses of either sense are actuallyinserted in the group but instead the corresponding number of pulses areeliminated from the input group, and the case where (D-N) is positiveand instead of each of said single pulses being inserted in the inputgroup, a pulse of the input group is given the weight or effect of twopulses.

Where the invention is employed for conversion either way between theimperial and metric linear scales, use is made of the fact that one inchequals 2.54 centimeters exactly. Such a ratio cannot readily be usedwhere the measurement to be converted is in the form of a seriessequence of electrical pulses each of which represents a distance ormovement (of, say, a machine tool or measuring probe) of fixed value,since fractions of pulses are impracticable units. But a more convenientratio occurs where each input pulse represents 0.001 inches and eachoutput pulse is to represent microns; for as 0.001 inches is equal to25.4 microns, the conversion ratio becomes 25.4/25, or 127/ I25. Thisratio is a particular example of the ratio D/N above referred to.

Imperial/metric (IIM) conversion can thus be achieved by replacing eachgroup of 125 imperial pulses by 127 metric pulses. As the term (DN) ispositive, being equal to +2, the conversion merely necessitates theaddition of two pulses to each input group.

For M/[ conversion, on the other hand, (DN)=-2, with the pulses now ofnegative sense; here the algebraic addition to each input group meansthe subtraction of two pulses from it. y

In order to make the conversion as smooth as practicable the two pulsesare added, or subtracted, singly, at locations which in the output pulsesequence are as evenly spaced with respect to one another as thenumerical values allow.

Thus in HM conversion the two pulses are spaced apart at l25/(l27-1r orabout 62, pulses of the input sequence. Convenient locations are after31 and 93 pulses of each group. This gives spacing of alternately 62'and63 pulses along the output train of contiguous groups.

Similarly. for M/I conversion. Here the approximate spacings are127/(125-127), or about 63 pulses, ignoring the negative sign of thedenominator. Thus the spacings are about the same as before, with thedifference that each single pulse is subtracted fromthe input sequencerather than added to it.

Other conversion ratios, some of which are referred to later, may alsobe used. A

Thus, very broadly, the conversion means according to the invention forl/M conversion in the ratio 127/125 includes: (a) some sort of acounter, conveniently ofthe ring kind, to count each input pulse andidentify each group of I25; (b) a detector stage so connected to thevarious digit stages of the counter as to identify-that is, to respondby generating a control signaleach location in the input group where apulse is to be added; and (c) operative means arranged to be controlledby the control signals to perform the effective algebraic addition ofthe single pulses to each input group at the locations defined by thedetector stage. In the present instance the operative means includes apulse generator which in response to each signal generates a singlepulse and somehow adds it to the input group of pulses without causingpulse loss by overlapping. To ensure that such loss is prevented, adelay stage may be necessary to retain the single pulse until a spacebetween the input pulses is available for it.

Similar arrangements are made for M/l conversion, except that as theadded pulses are now of negative sense the generator of the operativemeans is replaced by an inhibit or other form of logical gate betweenthe input and the output channels; when operated by the control signaleffects the algebraic addition by causing a pulse of the input sequenceto be eliminated at each appropriate location.

The pulses of the input sequence are not required to be regularly spacedin time. This is particularly so with machine tool applications, whereeach sequence controls the backward and forward movement of a tool orworkpiece in one of two or three orthogonal directions.

Embodiments of the invention will now be described by way of example in'more detail, with reference to the accompanying drawings in which FIG.1 is a schematic diagram of an embodiment of the invention arranged forI/M conversion,

FIG. 2 is a similar diagram to FIG. l but in respect of MII conversion,

FIG. 3 shows suitable circuit details for stages shown generally in FIG.1,

FIG. 4 is a schematic diagram of a modified form of the arrangement ofFIG. 1,

FIG. 5 shows the arrangement of FIG. 4 modified for M/l conversion, and

FIG. 6 shows the arrangement of FIG. 4 modified for a different kind ofcounter,

FIG. 7 shows in block form part of a stage of a further kind of counter,

FIG. 8 is a schematic diagram of a part of a counter made up of stagesas shown in FIG. 7,

FIG. 9 is a schematic diagram of a further part of the counter of FIG.8,

FIG. 10 is a schematic diagram of an embodiment of the invention forconversion in the UM direction which makes use of the counter of FIGS. 7to 9,

FIGS. 11 and 12 show waveforms to illustrate the operation of theembodiment of FIG. 10,

FIG. 13 shows part of the embodiment of FIG. 10 but modified forconversion in the M/I direction,

FIGS. 14 and 15 show waveforms to illustrate the operation of theembodiment of FIG. 13,

FIGS. 16 and 17 show modifications of the apparatus of FIG. 9 to suitother conversion ratios,

and FIG. 18 shows in block form a further embodiment.

The invention will first be described by way of example with referenceto FIG. 1 as used for converting in the UM direction.

The input pulses arrive over a channel 11 and are applied topulse-counting means in the form of a bidirectional binary ring counter12 of l25-pulse capacity. The counter is of the kind which has a singleinput and is conditioned to add or subtract by the biases applied to Addand Subtract leads A and S common to all stages.

Associated with the counter is a detector stage 13 arranged to identifythe respective pulse locations by detecting the pulse contents of thecounter which precede those locations, and in response supply a controlsignal over a lead 14 when the counter holds 31 pulses and over a lead15 when the counter holds 93 pulses. A diode decoding network of aconventional kind connected to each digit stage of the counter may servefor this purpose.

Leads 14 and 15 provide the inputs for an OR-gate 16 the output fromwhich is applied to a combined delay stage and amplifier 17.

Each pulse generated by stage 17 after the delay built into it isapplied as one input to an OR-gate 21 having as another input the inputsignals, delivered from channel 11 by a lead 22. The output lead 23 fromgate 21 may be considered the output channel of the apparatus. In thisembodiment it is applied as input to a bidirectional counter 24, whichis similar to counter 12 (and like it controlled over leads A and S) butof considerably greater capacity.

In operation, the input pulses, each of which represents a tool movementof l/l25th, or 0.001, inches in one or other direction according to thesign represented by the pulse, as prescribed by the bias on leads A andS, arrive in an irregularly spaced manner over the input channel 11. Inresponse, counter 12 adds them algebraically, according to the sign ofeach, identifying each group totaling 125 by cycling through itscontents from 0 back to 0. At the same time the input pulses are appliedby way of OR-gate 21 to counter 24, to be added or subtracted thereaccording to the bias on leads A and S.

Each time the count reaches the total 31, appropriate to a pulselocation, detector 13 responds by supplying a control signal by way oflead 14 and OR-gate 16 to stage 17, to generate a single pulse after aslight delay. This pulse is fed by way of OR-gate 21 and output channel23 to the counter 24, the delay in stage 17 being such as to ensure thatthe pulse is interpolated between successive pulses of the originalinput pulse sequence without risk of pulse loss due to pulse overlap orcoincidence. A single pulse is similarly interpolated each time thecounter reaches the number 93.

Where a pulse has been added as described in the precedingparagraph-when the counter reaches the total 31, sayand the input pulsesbecome negative, as prescribed by the bias on leads A and S, with theresult that both counters begin to count down, the return of counter 12to the total 31 again results in the generation and interpolation of asingle pulse, but as it is of opposite sign to the single pulseinterpolated during the upward count, this further single pulse has thedesired effect of cancelling out the earlier one.

Thus each successive input group has its algebraic total of 125 pulsesdelivered over the output channel with two pulses interpolated to bringthe total to 127. The required conversion has thus been carried out.

FIG. 2 shows the modification required for conversion in the M/ldirection-that is, where each input group of 127 pulses has to beconverted to 125. As the two single pulses have now to be subtractedinstead of added, stage 17 is dispensed with, and OR-gate 21 replaced byan Inhibit gate 25 arranged to be so controlled by the control signalfrom stage 13 as to block a pulse of the input group each time thecounter reaches the totals 31 and 92.

Both the above-described arrangements may be modifiedto suit the kind ofcounter which in place of the Add and Subtract controls of counters 12and 24 is provided with Add and Subtract input rails, the sign of eachinput pulse being indicated by the rail it arrives on. Where theconversion requires pulses to be added, as in the arrangement of FIG. 1,it is necessary to generate each of such supplementary pulses so as tohave the sign of the input pulse (32 or 93, in the particular examplequoted) which caused its generation. As described below with referenceto the corresponding arrangement of FIG. 6, this is convenientlyarranged by causing each input pulse to control the setting of abistable stage to a state representing the sign of that pulse, andapplying the output from the stage to cause the supplementary pulse (ifany) to be directed to the appropriate rail of the output counter.

Where the conversion requires pulses to be subtracted, the controlsignal is applied in parallel to two inhibit gates, one in each of thechannels between the input channel and the A and S rails of the outputcounter.

FIG. 3 shows a suitable decoder circuit for detector stage 13 in thearrangement of FIG. 1. For convenience of illustration it is assumedthat the counter is a four-stage binary counter and that thepulse-location numbers to be detected are 3 and l 1.

The stage includes two four-entry AND-gates 31 and 32. Gate 31 isdesigned to detect the number 3, or binary l (most significant digit onthe right); hence its four inputs are from the digit 0 outputs fromstages 2 and 2 and the digit l outputs from stages 2 and 2. Thus thegate passes a signal when the counter holds 3 pulses.

Similarly gate 32, to detect binary l 101, has one input from the digit0 output of stage 2 and the remaining inputs from the digit 1 outputs ofthe other stages. The outputs from these gates are respectively appliedover leads l4 and 15' to an OR- gate 16the equivalent of leads 14 and 15and gate 16 of FIG. 1.

A similar form of detector may also be used in the arrangement of FIG.2.

FIG. 3 also shows suitable apparatus for stage 17 of FIG. 1. Thisincludes two cascaded monostable stages 33 and 34. Stage 33 is arrangedto be triggered (set) by the control signal from detector 13 and itselfto trigger stage 34 on resetting. The output from stage 34 is applied toOR-gate 21. Thus the two monostable stages define by the durations oftheir respective unstable states the extent of the delay period (betweenthe initiation of the control signal and the initiation of a pulse to beadded to the train) and the width of the added pulse.

Some delay will necessarily occur between the initiation of a controlsignal and its effect in adding or subtracting a pulse. If during thisdelay period the sense of the input pulses should reverse, a pulse maybe wrongly added or wrongly subtracted. For example, if the controlsignal is initiated to delete a pulse during a forward count, and theinput train reverses during the delay period, the control signal willonly become effective after reversal, and by subtracting a pulse fromthe then negative train will make the deletion have the incorrect effectof an addition.

One way to prevent such misoperation is to arrange for stage 13 todetect two adjacent numbers-for example, 32 and 33, 93 and 94and employa simple gating network responsive to the sign of the input pulses andto the input pulses themselves to ensure that the control signal isgenerated at each lower number-32 and 93-on an upward count but at eachhigher number-94 and 33on a downward count and to delay the controlsignal and hence the effective addition of a pulse until the arrival ofthe next input pulse.

This may be arranged as in FIG. 4, which shows the circuit of FIG. 1suitably modified.

To simplify the explanation of this embodiment of the invention andthose to be described later, the convention will be adopted of referringto leads and output points as energized when representing digit 1 andunenergized or at zero output when representing digit 0; whereas inpractice the reverse may be the case, or the energization may beuninterrupted and the respective digits represented by different extentsor senses of energization.

Similarly as regards the Add/Subtract bias leads: only the lead A isenergized when addition is required, and only the lead S forsubtraction.

An And gate will be referred to as open" when all its inputs areenergized, closed if at least one input is not, and alerted" if all itsinputs except one are energized.

OR-gate 16 of FIG. 1 is now in two parts 16A and 168. Gate 16A receivesas inputs from detector 13 control signals over leads 14A and 15A whichare energized when counter 12 holds the numbers 32 and 93. The outputfrom this gate is applied as one of the inputs to a two-entry AND-gate41A. The other input to gate 41A is derived from the Add bias lead A,and its output is applied to an OR-gate 42.

Gate 168 similarly combines the control signals on leads 14S and 15S,responsive when the counter holds the numbers 33 and 94, and appliesthem to OR-gate 42 by way of an AND- gate 418, controlled from bias leadS.

The output from OR-gate 42 is applied as one input to an AND-gate 43having as a second input a connection from the input lead 11. The outputfrom gate 42 is applied to the combined delay and pulse generator stage17.

In operation, when the number 32 is reached on an upward count, theresulting control signal generated by detector 13 finds gate 41A alreadyalerted by the Add bias on lead A. But as the initiating pulse (the32nd) has now ceased, the control signal is blocked at the next AND-gate43 until the next pulse (the 33rd) arrives.

If therefore the direction of count should reverse between those inputpulses, no harm would be done, for the reverse of the bias on leads Aand S would close gate 41A before the control signal could becomeeffective, with the result that the next input pulse is blocked at gate43.

If on the other hand reversal should take place after the 33rd pulse hadarrived, the control signal initiated by the preceding pulse would havebeen effective in adding a pulse. But the reversal would allow thecontrol signal in respect of the 33rd pulse to become effective too, byway of gate 418, and being of the opposite sense to the one just added,would cause it to be cancelled. In other words, the pulse added at theforward count would be eliminated by subtraction at the reverse count.

Where conversion is in the M/l direction, where pulses are to besubtracted rather than added, the arrangement of FIG. 4 may be as shownin FIG. 5. The output from gate 42 is applied direct to the controlpoint of inhibit gate of FIG. 2. As no pulses are to be added, a gatecorresponding to gate 43 of FIG. 4 to allow the next input pulse torelease the control signal, is unnecessary.

Where the counter is of the kind having only two inputs for pulses to beadded or subtracted respectively, the arrangement of FIG. 4 may bemodified as shown in FIG. 6.

As there are now no bias lines to determine in advance the sign of theinput pulses and hence the sign of the added pulses, each input pulsearriving over the Add line 11A or the Subtract line 115 is applied tocontrol the setting of a bistable stage 51. In one of its states-the Setstate, say-stage 51 represents Add, and in its reset state Subtract. Thestage thus staticises the sign of the last input pulse.

The output from OR-gate 42 (FIG. 4) is applied to stage 17 direct. Inthis arrangement gate 43 of FIG. 4 is not needed, for the input pulsesnow arrive over leads 11A or 118 at gates 41A or 415. The output fromstage 17 is applied as one of the inputs to each of two-entry ANDgates52A and 528, to the other entries of which are applied those outputsfrom stage 51 that are energized to represent its Add (Set) and subtract(Reset) states. The outputs from gates 52A and 525 are applied to theAdd and Subtract rails of the output counter 24 by way of OR-gates 53Aand 535 having leads 11A and 118 as the other inputs.

Little description of the operation is necessary. At the end of eachinput pulse, stage 51 remains representing the sign of that pulse andhence the sign of the pulse to be added, if any. By alerting theappropriate one of gates 52A and 525, the output from stage 51 causesthe additional pulse to be directed to the appropriate rail of theoutput counter 24.

A decoder 12 of the type described with reference to FIG. 3, requiringas it does two output leads from each digit stage of the counter, may beundesirably complex where the counter has more than a few digitstages-cg, where for a count of I25 seven digit stages are needed. Asomewhat neater and simpler decoder may be designed in reliance on theknown property of binary counters that in an upward count only one stagechanges from 0 to l at each input pulse though several stages maysimultaneously change from 1 to 0, and only one stage changes from 1 toO on a downward count.

Further, in the mth stage of an n-stage binary counter the number ofsuch changes during a cycle of the counter is 2""" and in each stage thechange points from O to l or I to 0 are uniformly distributed over thecycle. It is thus possible to select, for the purpose of identifyinglocations in the pulse sequence for adding or subtracting pulses asdescribed above, any number of change points in the cycle by detectingthe changes from 0 to 1 during addition, or I to 0 during subtraction,in any one stage or combination of stages.

Taking the numerical example already used, the 32nd (i.e., 2 th) pulsemay be detected by detecting the change from 0 to l in the sixth digitalstage; this may be done by differentiating the output from that stageand selecting the positive-going spike of the two which result.

The 93rd pulse is less easy to detect; but by choosing instead the 96th(i.e., 2 +2 identification may be obtained from the sixth and seventhstages by AND-gating the positive pulse from the leading edge of thesixth stage output with output from the seventh stage.

A further simplification results if the binary counter 12 used is of thesynchronous type in which each signal pulse is applied to all the digitstages simultaneously and only those respond by changing state which areenabled (that is, alerted or primed) by signals derived from the statesof earlier stages before the pulse arrived.

Such a counter may be of the kind which uses for each digit stage theparticular form of bistable stage known as a J K flipflop.

Such a digit stage D (FIG. 7) includes control input points I and K, aclock input point C, and two output points Q and NO (not O). For thepurpose of the invention the J and K are commoned, the control signal isapplied to both, and the circuit has the following properties:

a. The two stable states are: (i) Q energized but NO unenergized, thestage as a whole holding digit 1; (ii) the reverse of state (i), thestage now holding digit 0. These will be referred to as the Set andReset states respectively.

b. When the control signal is O, the common input JK is unenergized; anyinput clock pulse arriving at point C is ineffective, leaving theoutputs in the Set or Reset state they happened to be in when the pulsearrived. The stage may be said to be disabled--that is, unresponsive toan input pulse at point C-by the control signal at J K.

c. When the control signal is l, the common input I K is energized; aninput pulse arriving at C causes the stage to reverse its state. Thecontrol signal is thus maintaining the stage enabledready to respond tothe next input pulse.

Digit stages D D and D of a counter made up of seven such .lK stages areshown in FIG. 8.

The J K flip-flop D for the units stage has the common input points Jand K supplied over a control lead RD A connection is made to the Cinput point from the pulse input lead 11, which is common to all sevenstages. The output is supplied over leads 0,, and NQ,,.

Lead O is connected as one input to a three-entry AND- gate 61 the otherentries to which are supplied by the Add bias line A and a lead 63.

Similarly lead N0 is connected as an input to an AND-gate 62 havingfurther inputs from Subtract lead S and lead 63.

The outputs from gates 61 and 62 are applied as inputs to an OR-gate 64.

The output from gate 64 is applied over a control lead RD. as thecombined J K control input to stage D Except for deriving its control JK input from stage D,, and the third inputs to its AND-gates 71 and 72from lead RD instead of from lead 63, stage D, is similar to stage D andsupplies a control signal to stage D by way of gates 71 and 72, anOR-gate 74, and lead RDQ.

Stages D to D (not shown) are exactly similar to stage D except thateach OR-gate corresponding to gate 64 has a third entry from a lead 65.Stage D is also similar, except that, as it is the last stage, two ANDgates corresponding to gates 71 and 72 of stage D, are not required.Each of these remaining stages includes an input from lead 65 to an ORgate corresponding to gates 64 and 74.

The operation will now be described for the particular case of an upwardcount from zero to 125, or binary 101 l l 11 (Note the binary numbersquoted in this specification have the least significant digit on theleft.

Until that total is reached, as described below with reference to FIG.9, leads RD and 63 are steadily energized, whereas lead 65 isunenergized. This energization of lead RD holds stage D,, in its enabledcondition throughout the count.

In the quiescent stage of the counter, holding the number zero, eachstage is in its Reset stage. As already mentioned, stage D,, is enabled.On the other hand stage D is disabled because (a) gate 61 is closedsince lead O is unenergized; and (b) gate 62 is closed because bias leadS is unenergized. Thus neither of the inputs to gate 64 nor its outputlead RD, is energized. As at this stage lead 65 is also unenergized, allthe higher stages are similarly disabled, each holding digit 0.

The first pulse to arrive is applied by lead 11 to the C inputs of allseven stages but finds only stage D enabled. The pulse thereforereverses the stage, leaving it still enabled but in its Set stage and soenergizing lead 0,, rather than N0 With gate 61 thereby opened, stage D.is enabled, though as yet remaining in its Reset state, ready to respondto the next pulse. The remaining stages stay disabled.

The second pulse, finding stage D,, still enabled, switches it back toits Reset state, closing gate 61. As stage D, is also enabled, thepulse, acting by way of the direct connection from lead 11, switches itto Set. In this condition stage D1 is no longer enabled, because gate 61is now closed. The overall condition is that stage D,, is enabled (asalways, until the end of the count) but is now in its Reset stateholding digit 0; stage D, is disabled but Set, so holding digit 1 andenergizing lead 0, and all the other stages are disabled and Reset. Thusthe count reads 0100000.

The third pulse merely switches D,, to Set, reopening gate 61 andreenabling stage D1, leaving it still holding digit 1. With output leadQ, still energized by stage D, a path is completed through the reopenedgate 61 and gates 64, 71, and 74 to enable stage D, (not shown). Bothstages D,, and D, now hold digit 1, with the counter reading l 100000.

The fourth pulse finds each of stages D,, to D enabled and so reverseseach of them, bringing D and D to Reset but D to Set, and leaving onlyD,, enabled: 0010000.

Suppose now that a pulse arrives to be subtracted -that is, with lead Senergized rather than lead A. The effect of this reversal of theAdd/Subtract bias is to enable both stages D and D,,: D, by way of gate62 (now open, since leads NO and S are energized as well as lead 63) and64, and D, by way of gates 62, 64, and 72. As all three stages areenabled before the pulse arrives, the effect of it is to reverse each ofthem, and so change the number held from 0010000 to 1 100000. So long asthe counter remains conditioned for subtraction, only stage D,, isenabled, the higher stages being blocked by gates 61 and 62 because ofthe unenergized condition of leads A and NQ respectively. The next pulsewould then change the number to 0100000. If the Add/Subtract bias shouldbe changed to Add while the counter held the number 1 100000 all threestages would be enabled, and the next pulse would be added as the fourthpulse was as described in the preceding paragraph.

It will therefore be seen that a stage is disabled on an upward countuntil each lower stage holds digit 1; and on a downward count until eachholds digit 0.

The operation is similar in response to further pulses of either sign.

As the counter has to have an effective total of 125 pulses rather thanits natural total of 127, arrangements have to be made to force itsReset to zero on receipt of the 125th pulse in an upward count, and torevert from 0 to 125 on receipt of the first pulse after zero has beenreached on a downward count. This is the function of leads RD,,, 63, and65, and their sources of energization, in the arrangement justdescribed. They act by detecting the arrival of the 124th pulse on anupward count and in response to the next pulse switch to their Resetstate all stages that are in their Set state when the pulse arrives. As124 corresponds to the binary number 001 l l l 1, the task amounts tothe resetting of each of stages D to D,, when the total 125 is reached.Similarly the task when zero is reached on a downward count is to switchthose stages to their Set state when the next pulse arrives. Suitableapparatus for doing this is shown in FIG. 9.

Block D represents digit stage D,, of FIG. 8 together with its outputAND-gates 61 and 62. Block D, represents stage D,, together with itsinput OR-gate 64 and output AND-gates 71 and 72. The remaining blocksare similar to block D, except that block D, has no output AND gates.

A six-entry AND-gate 81 has one input from lead A (Add) and one eachfrom output leads O to 0,. An eight-entry AND-gate 82 has one input fromlead S (subtract) and one each from output leads NO, to N0 The outputsfrom these gates are combined at an OR-gate 83. The output from gate 83is connected to lead 65 and, by way of a negater stage 84 and lead 85,to leads RD,, and 63. A further output from negater 84 is supplied overa lead 86 to apparatus which is described below with reference to FIG.10.

In operation, when the counter holds zero with the Add bias lineenergized, gate 81 is closed because none of the output leads O to Q, isenergized. Gate 82 is also closed, because although leads NO, to NQ areall energized, lead S is not. Thus the output from gate 83 isunenergized. This condition is reversed by negater to supply anenergizing signal over lead 85 to the control lead RD and to lead 63, tomaintain stage D,, enabled and gate 61 alerted throughout the count asabove described.

During a subsequent upward count, gate 82 remains closed. Gate 81 alsoremains closed-until the total 124 is represented by the energization ofeach of leads Q, to Q The resulting output from gate 83, reversed bystage 84, removes the signal from each of leads RD,, and 63. On theother hand the energization of lead 65, acting by way of OR-gate 74 andthe corresponding gates of the higher stages, switches each of stages Dto D,, from digit 1 to digit 0 i.e., to its Reset state. All stages nowhold zero.

The operation is similar when zero is reached on a downward count; thistime it is gate 81 that remains closed, and gate 82 opens when each ofstages NO,, to NO, holds zero. Lead 65 is also energized as before, butthis time the switching action which it exerts on stage D, to D is toreverse them from digit 0 to digit 1, leaving stages D,, and D, holdingzero. Thus the counter holds the binary number 001 l l l l or decimal124.

The modification necessary to the circuit of FIG. 1 where the counter 12is of the JK kind described above with reference to FIGS. 7 to 9 isshown in FIG. 10, using the same reference numerals for componentscorresponding to those of FIG. 1 and assuming again that conversion isin the direction I/M with 125 pulses in each input group.

As the pulses that are to be detected are the 32nd and 96th of eachgroup, the digit stage which the detector has to respond to is stage D5.The control signal for the stage is derived over a lead RD which hereacts the part of detector 13, from an OR-gate 94 corresponding to gates64 and 74 of stages D, and D see FIG. 8. The outputs over leads 0,, andN0 assist in controlling output AND-gates 91 and 92 corresponding togates 71 and 72 of stage D,.

Corresponding to gates 41A and 415 of FIG. 4 are two three-entryAND-gates 93 and 95. Gate 93 has inputs from leads A, N0 and RD,,whereas gate 95 has inputs from leads S, Q and RD The outputs arecombined at an OR-gate 42', corresponding to gate 42 of FIG. 4, andapplied as one of the inputs to a four-entry AND-gate 96. The remaininginputs to the gate include a connection from lead 11, thereby renderingthe gate the equivalent of gate 43 of FIG. 4, lead 86 (FIG. 9) and alead 97 the energization of which is manually controlled. The outputfrom gate 96 is applied to pulse generator 17,

which may take the form described with reference to FIG. 3. The delayedpulse thereby derived is applied as one of the in puts to OR-gate 21having the pulses on lead 22 (FIG. I) as the other input and applyingits output over channel 23 to counter 24, all as described withreference to FIG. 1.

The remaining six stages D to D and D may be as described above withreference to FIG. 8, except that the Q and NO outputs are only used tocontrol the local AND-gates and the switching stages 81 and 82 of FIG.9.

The operation of this equipment will be described with reference to thesignal waveforms of FIG. 11. These show at (a) the input pulses arrivingover leads 11 and 22 at random, with the 31st and 32nd pulses labeledP31 and P32. Waves (b), (c), and (d) represent the signals on leads Q Nand RD waves (e) and (f) show the outputs from gates 42 and 96 bothwaves representing the control signal; wave (g) shows the pulsegenerated by stage 17, and wave (h) shows the train of pulses deliveredby gate 21 to the output channel 23.

It is assumed that the Add/Subtract bias leads A and S are in their Addcondition-that is, with only lead A energized.

Before the arrival of pulse P31, stage I) is holding digit 0 and so isenergizing its output lead NQ rather than (l -see waves (b) and (c). Thestage is disabled by a zero signal on lead RD wave (d)because one atleast of the five lower stages is not holding digit 1. Thus gates 93 and95 are both closed, the outputs from gate 42, gate 96, and pulsegenerator 17 are also zerowaves (e) to (g)-and the incoming pulses arepassing uninterruptedly through gate 21 to channel 23 and counter 24wave(h). As regards gate 96, the input to it over lead 86 is energized fromOR-gate 83 and negater 84 in the absence of outputs from gates 81 and 82as explained with reference to FIG. 9; lead 97 is also energized, undermanual control; and signals are awaited from gate 42 and lead 1 1 beforethe gate can open.

With the arrival of the 31st pulse the number held by the counter as awhole is 1111 100. Hence each of the five stages below stage D holdsdigit 1. In consequence stage D is enabled by the signal on lead RDinitiated in synchronism with trailing edge of pulse P3l-wave (d), butas yet remains holding digit 0.

Each of the three entries to AND-gate 93 (including lead N0 is thusenergized and the gate transmits through gate 42 a control signal ofwaveform (e). This however is blocked by gate 96 which is closed in theabsence of a signal on lead 11 since by this time the signal P31, whichinitiated by its trailing.

edge this control signal from gate 42, has itself ended. The stage isthus ready for pulse P32, with gate 96 fully alerted.

When that pulse arrives, to switch stage D to digit 1, its leading edgecompletes the entries to gate 96 and so passes as waveform (f) to stage17, which it triggers to generate a pulse P32wave (g)-after a delay DELto follow pulse P32 in the output trainwave (h)-delivered over theoutput channel 23 to counter 24. This operation of stage 17 is exactlyas described above with reference to FIG. 3. The delay is long enough toseparate pulse P32 from pulse P32 without any overlap but short enoughto ensure that pulse P32 is added in advance of the next pulse P33 atthe least possible pulse spacing of the input pulse sequence.

It will be seen that the control signal derived from detector 13-thatis, over lead RD -is held up at gate 96 until the arrival of the nextinput pulse, just as in the arrangement of FIG. 4 the control signal isheld up at gate 43, thereby similarly preventing misoperation due to areversal of pulse sense.

A further result of pulse P32 is to Reset each of the five lower stages,the number being new 0000010. Stage D is thus disabled by the return tozero of the signal on lead RD -wave (d)and remains with its output leadQ energized to represent digit 1.

Stage D remains in that condition until the 63rd pulse reenables it,ready to cause the 64th pulse to switch on the last stage D,,. Thistime, however, no supplementary pulse is generated because the signal onlead RD, is unable to open either gate 93 (as lead N0 is unenergized) orgate 95, since lead S is unencrgized.

For the next 31 pulses stage D remains disabled and holding digit 0exactly as it did during the first 3 l. The th pulse reenables the stageexactly as did the 31st, and the 96th pulse results in the generation ofa supplementary pulse exactly as did the 32nd.

Thus supplementary pulses are generated and inserted at intervals of(9632)=64, and (l2596+32)=61 pulse intervals.

The effect of the signal on lead 86 is to close gate 96 during each ofthe special counter switching conditions represented by the opening ofgate 81 or 82 in the circumstances described with reference to FIG. 9and so prevent the accidental addition of a pulse during one of theforced resets of counter 12 above described.

The effect of the signal on lead 97 under manual control is to allow thegate to be closed continuously at will whenever it is desired to arrestthe conversion andinstead transmit the input pulse sequence to theoutput channel unmodified.

the operation of the circuit in counting down is as follows.

The waveforms of FIG. 11 are modified as shown in FIG. 12, with (h) thepulses proceeding to counter 24 for subtraction. It is assumed that some34 pulses have previously arrived for addition, and been passed intocounter 24, together with a supplementary pulse added after the 32ndpulse as above described. Thus counter 24 holds 35 pulses whereascounter 12 holds 34, or binary 0100010.

Lead S is now energized instead of lead A.

The next pulses to arrive are therefore for subtraction. They arelabelled P1, P2, P3, etc., in FIG. 12in the order of their arrival. Atthe foot of the diagram are inserted the numbers left in the respectivecounters after each pulse has been absorbed.

Pulse P1 drops the counters to 34 and 33; pulse P2 drops them to 33 and32. With counter 12 thus holding binary 0000010, stage D is enabled-wave(d)holding digit 1, with lead 0 energized.

Reverting now to FIG. 10, the leads Q and S are energized as well aslead RD causing gate 95 to pass a signal wave (e)-through gate 16 tofully alert gate 96 in readiness for the next pulse P3. That pulse,which itself on arrival reduces the counts to 32 and 31, results in thegeneration of a supplementary i lse P3 which, being also forsubtraction, reduces the number in counter 24 to 3l while counter 12remains holding 31. The supplementary pulse added an upward count hasthus been cancelled on the downward count, and further subtractivepulses step the counters downwards in numerical correspondence.

If the counting direction is changed from Add to Subtract after the 31stadditive pulse P31 had arrived, and accordingly stage D is enabledholding digit 0 and with gate 93 alerted, the deenergization of lead Acauses gate 93 to close while gate 95 remains closed because of the zerosignal on lead Q Thus the next pulse to arrive-the first forsubtraction-finds gate 96 closed by the zero signals from both gates 93and 95 and so does not result in the generation of a supplementarypulse.

There is no third condition of sign reversal, for the mere sign changebetween pulses P32 and P32, or P3 and P3, has no effect until the nextpulse arrives; and, as already stated, the delay between a supplementarypulse and the preceding one is too short for a pulse to arrive duringthat delay interval.

FIG. 13 shows the alterations necessary for the circuit of FIG. 10 wherethe conversion is in the M/I direction, so that pulses have to besubtracted rather than added. The changes closely correspond to thosebetween FIG. 1 and FIG. 2. As gating by the input pulses is notrequired, gate 96 of FIG. 10 is now a three-entry gate 96, with only theinputs on leads 86 and 97 as well as that from gate 42. The output isapplied to control the inhibit gate 25 in the path between leads 22 and23 as in FIG. 2.

For addition, the corresponding waveforms are shown in FIG. 14. Waves(a) to (e) are the same as in FIG. 11. Being free from control by theinput pulses, gate 96 delivers a signal which is coterminous with theenabling signal RD wave (f). As these signals do not end until the endof pulse P32, the latter is eliminated by the inhibiting signal fromgate 96 as shown in wave (h) where the deleted pulse is indicated inbroken lines.

FIG. 15 shows the waveforms corresponding to those of FIG. 14 toillustrate the effect of a change from Add to Subtract after the inputtrain had delivered 34 pulses. This time the deletion of a pulse hascaused counter 24 to hold one less than counter l233 pulses as against34. By the time pulses P1 and P2 have been absorbed, counter 12 holds 32and is enabled by a signal on RD wave (d)with the result that gate 25 isclosed in readiness to delete pulse P3. The result of thus deleting asubtractive pulse is to add a pulse and so counteract the pulse deletionmade during the upward count. From pulse P3 downwards, therefore, thetwo counters are in numerical correspondence.

If reversal should come after the stage has been enabled by pulse 31,both AND-gates 93 and 95 are closed by the zero signals on leads A and Qas in the arrangement of FIG, in consequence the count turns down beforea pulse has been subtracted.

The reversal operations are similar in the region of the 96th pulse.

Conversion in the M/I direction also requires some alterations to thearrangements of FIG. 9 so as to force the reset at 127 rather than 125.As shown in FIG. 16, the only material difference is that as the numberto be detected during an upward count is binary 01 I 1 111, rather than00111 I 1, the sixentry AND-gate 81 of FIG. 9 is replaced by aseven-entry AND-gate 101 to which the extra input is lead 0,. Gate 82,having again to detect a total zero, is as before. The only other changeis that output lead 65 from OR-gate 83 is now extended to the inputOR-gate 64 (FIG. 8) of stage D,.

Other conversion ratios may be used. Thus where it is desired to converta series sequence of pulses each of which represents 1/l,000 inches to asequence of pulses each representing 20 microns, the conversion ratio is100 to 127, with (DN) =27. A seven-stage binary counter is again needed,though its scope has to be severely curtailed. Rather than force a resetfrom 100 to zero, it may be preferable to centralize the used range ofthe counter to the region from to ll5,orbinary 1111000to 1100111.

The circuits of FIGS. 9 and 16 are therefore modified as shown in FIG.17.

A five-entry AND-gate 111 has one input from the Add lead A and furtherinputs from leads Q,, 0,, Q and Q It thus detects the number 1 14 orbinary 01001 11. In response, and acting by way of OR-gate 83 and lead65, it renders all stages except D enabled, so that the 115th pulseswitches the counter to binary 1111000 or 15.

To detect 15 on a downward count a four-entry AND-gate 112 has an inputfrom the Subtract lead S and inputs from leads N0 N0 and N0 Its responsealso acts by way of lead 65 so as to render all stages except D enabled.There is no ambiguity in relying only on the three most significantdigit stages for this detection as the counter never operates belowbinary 1111000.

In this arrangement the output from gate 83 by way of negater 84 andlead 85 is applied to the control and the AND gate inputs of stage Drather than stage D as in the embodiments previously described.

Where (DN) is positive and the output pulses are applied to a counter,such as counter 24, it is not necessary for each supplementary pulse tobe literally added to the input pulses; instead, each may be effectivelyadded by so applying the control signal as to cause the next input pulseto have the effect of two at counter 24.

A suitable modification of the arrangement of FIG. 10 is shown in FIG.18 wherein counter 24 is assumed to be of the .IK flip-flop form asdescribed above for counter 12 with reference to FIG. 8. To simplify thedescription, therefore, the first stage of counter 24 is depictedsimilarly to that of counter 12, but with the corresponding referencesprimed.

Stage 17 and gates 21 and 96 are not required; lead 11 is connected tothe digit stages of counter 24 direct; and the control signal ofwaveform (e) (FIG. 11), derived by gate 16, is applied as a third inputto OR-gate 64 and to the control point of an Inhibit gate 121 insertedin lead RD,,.

In operation, leads Rd',, and 63' are positively energized while thecounter is in action. The effect of each control signal is to close gate121, thereby disabling state D',,, and pass by way of gate 64 to enablestage D I instead. Thus the next pulse of the input series arriving overlead 11 actuates stage D, rather than stage D and so has the weight oreffect of two pulses, i.e., it is counted as two.

If when the control signal is derived, stage D is already enabled, thesignal leaves it enabled, and merely disables stage D What we claim is:

1. Scale conversion apparatus for converting an input series sequence ofelectrical pulses of either sign significance, representing equalincremental quantities expressed in a particular measurement scale, toan output series sequence of pulses expressed in another scale, wherethe output/input scale ratio is D/N, comprising pulse-counting meansarranged to count the input pulses and identify each group totaling Nalgebraically, a detector stage responsive to the state of the countingmeans to identify in each group the locations for (DN) single pulsesspaced substantially evenly one another within the group and from thenearest corresponding single pulses of immediately adjacent group(s),and develop a control signal with respect to each location, andoperative means arranged to be controlled by those control signals so asto effectively add the single pulses algebraically, in dependence on thesign of (DN), to each input group at the locations identified by thedetector stage, thereby deriving as said output sequence an output grouptotalling D pulses algebraically for each of said input groups of Npulses together with gating means responsive to the sign of the inputpulses and to the input pulses themselves, for delaying each sucheffective addition of a single pulse until the arrival of the next inputpulse, thereby preventing such addition if a change of sign should occurafter generation of the corresponding control signal but before suchaddition has taken place.

2. Apparatus as claimed in claim 1 wherein the pulse-counting meansincludes a bidirectional binary synchronous counter and said detectorstage is arranged to develop a said control signal each time aparticular one of the digit stages of the counter changes from digit 0to digit 1 on an upward count or from digit 1 to digit 0 on a downwardcount, thereby in each case identifying one of said locations.

3. Apparatus as claimed in claim 2 wherein the detector stage includes agating network arranged to derive a control signal each time a pulse ofthe input group finds that particular digit stage enabled and holdingeither digit 0 on an upward count or digit 1 on a downward count.

4. Scale conversion apparatus for converting an input series sequence ofelectrical pulses of either sign significance, representing equalincremental quantities expressed in a particular measurement scale, toan output series sequence of pulses expressed in another scale, wherethe output/input scale ratio is DIN and (DN) is positive, comprisingpulse counting means arranged to count the input pulses and identifyeach group totalling N algebraically, a detector stage responsive to thestate of the counting means to identify in each group the locations for(DN) single pulses spaced substantially evenly from one another withinthe group and from the nearest corresponding single pulses ofimmediately adjacent group(s), and develop a control signal with respectto each location, and operative means arranged to be controlle; by thosecontrol signals so as to effectively add the single pulsesalgebraically, in dependence on the sign of (DN), to each input group atthe locations identified by the detector stage, said operative meansincluding means to be operated by said control signal to give the inputpulse at each of said locations the effect of two pulses therebyderiving as said output sequence an output group totalling D pulsesalgebraically for each of said input groups of N pulses.

5. Scale conversion apparatus for converting an input series sequence ofelectrical pulses of either sign significance, representing equalincremental quantities expressed in a particular measurement scale, toan output series sequence of pulses expressed in another scale, wherethe output/input scale ratio is D/N, comprising pulse-counting meansarranged to count the input pulses and identify each group totalling Nalgebraically, said pulse-counting means including a bidirectionalbinary synchronous counter and said detector stage is arranged todevelop a said control signal each time a particular one of the digitstages of the counter changes from digit to digit 1 on an upward countor from digit 1 to digit 0 on a downward count, thereby in each caseidentifying one of said locations, a detector stage responsive to thestate of the counting means to identify in each group the locations for(DN) single pulses spaced substantially evenly from one another withinthe group and from the nearest corresponding single pulses ofimmediately adjacent group(s), and develop a control signal with respectto each location, and operative means arranged to be controlled by thosecontrol signals so as to effectively add the single pulsesalgebraically, in dependence on the sign of (D-N), to each input groupat the locations identified by the detector stage, said operative meansincluding connections for causing the control signal to disable thecounter stage of least significance and enable the next higher stage (ifnot already enabled), thereby causing the next input pulse to have theeffect of two pulses thereby deriving as said output sequence an outputgroup totalling D pulses algebraically for each of said input groups ofN pulses.

1. Scale conversion apparatus for converting an input series sequence ofelectrical pulses of either sign significance, representing equalincremental quantities expressed in a particular measurement scale, toan output series sequence of pulses expressed in another scale, wherethe output/input scale ratio is D/N, comprising pulse-counting meansarranged to count the input pulses and identify each group totaling Nalgebraically, a detector stage responsive to the state of the countingmeans to identify in each group the locations for (D-N) single pulsesspaced substantially evenly from one another within the group and fromthe nearest correspondIng single pulses of immediately adjacentgroup(s), and develop a control signal with respect to each location,and operative means arranged to be controlled by those control signalsso as to effectively add the single pulses algebraically, in dependenceon the sign of (D-N), to each input group at the locations identified bythe detector stage, thereby deriving as said output sequence an outputgroup totalling D pulses algebraically for each of said input groups ofN pulses together with gating means responsive to the sign of the inputpulses and to the input pulses themselves, for delaying each sucheffective addition of a single pulse until the arrival of the next inputpulse, thereby preventing such addition if a change of sign should occurafter generation of the corresponding control signal but before suchaddition has taken place.
 2. Apparatus as claimed in claim 1 wherein thepulse-counting means includes a bidirectional binary synchronous counterand said detector stage is arranged to develop a said control signaleach time a particular one of the digit stages of the counter changesfrom digit 0 to digit 1 on an upward count or from digit 1 to digit 0 ona downward count, thereby in each case identifying one of saidlocations.
 3. Apparatus as claimed in claim 2 wherein the detector stageincludes a gating network arranged to derive a control signal each timea pulse of the input group finds that particular digit stage enabled andholding either digit 0 on an upward count or digit 1 on a downwardcount.
 4. Scale conversion apparatus for converting an input seriessequence of electrical pulses of either sign significance, representingequal incremental quantities expressed in a particular measurementscale, to an output series sequence of pulses expressed in anotherscale, where the output/input scale ratio is D/N and (D-N) is positive,comprising pulse counting means arranged to count the input pulses andidentify each group totalling N algebraically, a detector stageresponsive to the state of the counting means to identify in each groupthe locations for (D-N) single pulses spaced substantially evenly fromone another within the group and from the nearest corresponding singlepulses of immediately adjacent group(s), and develop a control signalwith respect to each location, and operative means arranged to becontrolled by those control signals so as to effectively add the singlepulses algebraically, in dependence on the sign of (D-N), to each inputgroup at the locations identified by the detector stage, said operativemeans including means to be operated by said control signal to give theinput pulse at each of said locations the effect of two pulses therebyderiving as said output sequence an output group totalling D pulsesalgebraically for each of said input groups of N pulses.
 5. Scaleconversion apparatus for converting an input series sequence ofelectrical pulses of either sign significance, representing equalincremental quantities expressed in a particular measurement scale, toan output series sequence of pulses expressed in another scale, wherethe output/input scale ratio is D/N, comprising pulse-counting meansarranged to count the input pulses and identify each group totalling Nalgebraically, said pulse-counting means including a bidirectionalbinary synchronous counter and said detector stage is arranged todevelop a said control signal each time a particular one of the digitstages of the counter changes from digit 0 to digit 1 on an upward countor from digit 1 to digit 0 on a downward count, thereby in each caseidentifying one of said locations, a detector stage responsive to thestate of the counting means to identify in each group the locations for(D-N) single pulses spaced substantially evenly from one another withinthe group and from the nearest corResponding single pulses ofimmediately adjacent group(s), and develop a control signal with respectto each location, and operative means arranged to be controlled by thosecontrol signals so as to effectively add the single pulsesalgebraically, in dependence on the sign of (D-N), to each input groupat the locations identified by the detector stage, said operative meansincluding connections for causing the control signal to disable thecounter stage of least significance and enable the next higher stage (ifnot already enabled), thereby causing the next input pulse to have theeffect of two pulses thereby deriving as said output sequence an outputgroup totalling D pulses algebraically for each of said input groups ofN pulses.